1. Field
Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a semiconductor device and an operation method thereof.
2. Description of the Related Art
In general, a semiconductor device such as dynamic random access memory (DRAM) includes a great number of memory cells, and each of the memory cells includes a switching transistor and a capacitor serving as a data storage. Since a leakage current occurs due to the structure of the memory cell such as a PN junction of the transistor, data stored in the capacitor may be lost. Thus, the semiconductor device requires a refresh operation for restoring data in a memory cell before the data is lost. Hereafter, the refresh operation is referred to as a normal refresh operation.
The normal refresh operation includes an auto refresh operation and a self refresh operation. The auto refresh operation refers to an operation mode in which the semiconductor device performs a refresh operation in response to a refresh command applied from an outside. The self refresh operation refers to an operation mode in which the semiconductor device performs a refresh operation while sequentially changing an internal address in response to a refresh command applied from the outside.
Recently, an additional refresh operation is performed on a row (or a word line) in which the corresponding cell data are highly likely to be lost due to a row hammering (or a word line disturbance), in addition to the normal refresh operation. The row hammering refers to a phenomenon in which data of memory cells connected to a target row (i.e., a row with a large number of activations or a high activation frequency) and adjacent rows may be degraded due to the repeated activations on the row. Conventionally, counters are provided for the respective rows to prevent the data degradation by the row hammering, and an additional refresh operation is performed on a target row, which is activated a predetermined number of times or more, and adjacent rows, which are disposed adjacent to the target row. Such additional refresh operation is typically referred to as a target row refresh (TRR) operation (or a TRR mode). However, in order to supporting the TRR operation, a plurality of counters are required to be provided for the respective rows, and thus a circuit area occupied by the counters inevitably increases.